1. Technical Field
The present invention relates to electronic circuits in general, and, in particular, to latch circuits. Still more particularly, the present invention relates to a scannable latch having two cross-coupled NAND gates and a dynamic circuit.
2. Description of Related Art
Scan testings are commonly used to test the functionality of sequential logic circuits within integrated circuits. In typical scan testing approaches, some or all of the storage elements of an integrated circuit are modified to include scan inputs and outputs. In addition, the scan inputs and outputs of the storage elements are connected together in series to form a shift register, i.e., a scan chain. During a scan testing mode, the scan inputs are capable of being selected, and the scan chain are used to apply predetermined input signals to a set of combinational logic.
Specifically, during a scan operation, scan data is shifted into each of the storage elements. The output signals produced by the storage elements are then applied to the combinational logic, and signals produced by the combinational logic are captured by the storage elements. The captured signals produced by the combinational logic are subsequently shifted out of the storage elements of the integrated circuit, and are compared to expected values to determine if the combinational logic had performed a desired logic function.
Latches are typically considered as good candidates to be modified for the purpose of scan testings. This is because latches have relatively simple storage structures capable of transferring signals from inputs to outputs.
There are many ways to make such a latch scannable for the purpose of scan testings. However, the forward delay paths of a latch may be adversely affected if the latch is made scannable. The present disclosure provides a method for making a latch scannable while without sacrificing its forward path delays.